1. Field of the Invention
The present invention relates to a bit line contact structure and fabrication method thereof, and more specifically to a bit line contact structure using a spin-coating material as a pre-metal dielectric layer.
2. Description of the Related Art
As the integrity of integrated circuits increases, the size of semiconductor device is reduced. A dynamic random access memory (DRAM) device, for example, has a design rule for 64 MB DRAM of 0.3 μm or less, with design rule of 128 MB and 256 MB as low as 0.2 μm or less.
In a bit line contact structure, for example, when the line width is reduced to approximately 0.11 μm, the width of a drain region exposed by a bit line contact via is also reduced. When forming a conductive layer as bit line contact (CB) in the bit line contact via, either CB opening or word line-bit line shorts occur frequently, resulting in device failure, negatively affecting the yield and cost of the process.
Further, a conventional bit line contact structure uses boro-phosphosilicate glass (BPSG) as a pre-metal dielectric (PMD) layer even when the line width is reduced to approximately 0.11 μm, because BPSG has good hole-filling capability. However, when the line width is further reduced to about 0.070 μm to 0.090 μm, the width of the drain region exposed by the bit line contact via is also reduced to approximately 0.040 μm or less. The hole-filling capability of BPSG is insufficient to prevent voids in BPSG used as the PMD layer, further negatively affecting the yield and cost of the process.
Top views of FIGS. 1A through 1E and cross-sections of FIGS. 2A through 2E, 3A through 3E illustrate these problems in a conventional bit line contact structure and fabrication method thereof. Note that FIGS. 2A through 2E are cross-sections along line BB in FIGS. 1A through 1E, and FIGS. 3A through 3E are cross-sections along line CC in FIGS. 1A through 1E.
In FIGS. 1A, 2A, and 3A, first, a substrate 100, such as single crystalline silicon, having a transistor structure, is provided. The substrate 100 has a gate electrode 120 protruding from an active surface of substrate 100. A drain region 132 and source region 134 are disposed on the active surface respectively on two sides of the gate electrode 120. Gate electrode 120 is a word line, having a multi-level structure as required. Gate electrode 120 further has a spacer 126 on the sidewall, resulting in width of exposed drain region 132 between two neighboring gate electrodes 120 reaching approximately 0.040 μm when the design rule is reduced to about 0.070 μm to 0.090 μm.
In FIG. 1B, a dielectric layer 140, shown transparently for subsequent descriptions, is formed on substrate 100.
In FIG. 1C, dielectric layer 140 is patterned. Thus, a via 142 is formed exposing drain region 132.
In FIG. 1D, via 142 is filled with a conductive layer, respectively forming bit line contact pads 162a through 162c, electrically connecting to every drain region 132.
In FIG. 1E, finally, bit lines 190a through 190c, perpendicular to the word line of gate electrode 120, are formed using a metal layer. Bit lines 190a through 190c respectively electrically connect to bit line contact pads 162a through 162c. 
In FIG. 2B, a void 145 extending across at least two drain regions 132 appears in dielectric layer 140 during formation thereof using BPSG when the design rule is reduced to about 0.070 μm to 0.090 μm.
In FIG. 2C, when dielectric layer 140 is patterned, the former void 145 becomes void 145′ connecting two neighboring vias 142.
In FIG. 2D, the conductive layer fills both via 142 and void 145′ during formation of bit line contact pads 162a through 162c, resulting in bridging of the bit line contact pads 162a and 162c, must be isolated each other by isolation 110 and dielectric layer 140 in original design.
Thus, in FIG. 2E, when bit lines 190a through 190c are formed, bit line 190a electrically connects to bit line 190b. Thus, bit line-bit line shorts occur, negatively affecting the yield and cost of the process.
As mentioned above, width of the conventional exposed drain region 132 is approximately 0.040 μm or less, resulting in via 142 being extremely deep relative to the thickness of dielectric layer 140, about 0.3 μm to about 1.0 μm. The etching reaction during formation of via 142 slows as dielectric layer 140 at the bottom of via 142 is etched, resulting in the remaining dielectric layer 140 not being etched completely, at the bottom of via 142, thereby failing to expose drain region 132.
In order to completely remove the dielectric 140 from the bottom of via 142, over-etching is performed on dielectric 140, exposing drain region 132 as shown in FIG. 3C. Spacer 126 protects gate electrode 120 from electrically connecting to the subsequently formed bit line contact or bit line. Further, dielectric layer 140 is etched with high etch selectivity, of, for example, about 10 to 15, with respect to spacer 126 in order to prevent exposing the conductive layer of gate electrode 120 during etching of dielectric 140, when dielectric layer 140 is BPSG and spacer 126 is silicon nitride. When over-etching is performed to force etching of the dielectric 140 at the bottom of via 142, a part of spacer 126 may be removed, thereby exposing the conductive layer of gate electrode 120.
In FIG. 3D, bit line contact pad 162 electrically connects to the exposed conductive layer of gate electrode 120.
In FIG. 3E, bit line 190a electrically connects to the exposed conductive layer of gate electrode 120 through bit line contact pad 162. Thus, word line-bit line short occurs, negatively affecting the yield and cost of the process.